Frequency synthesizer circuits generally operate by using an oscillator which generates a high frequency clock signal and feeding the high frequency clock signal into a series of cascaded, programmable "divide-by-n" counter stages to generate a signal at a desired precise frequency. The counter stages are programmed by presetting the counter stages with a digital word which represents a value, N (or in some systems, the complement of N) then incrementing, or decrementing, as the case may be, the counter stages until either an overflow condition or an "all zero" condition is reached. The counter is then preset to N (or its complement) and the cycle is repeated. The value of N is typically determined by the equation: ##EQU1## where N is the divide ratio, f.sub.mc is the clock frequency, and f.sub.des is the desired output frequency. Equation (1) can be easily rearranged to yield: ##EQU2##
The frequency resolution, .DELTA.f, of such a system, which is the difference between the output frequency for N=N.sub.1, and the output frequency for N=N.sub.1 +1, is: ##EQU3## Substituting the N of equation (1) for the N.sub.1 of equation (3) yields: ##EQU4## Rearranging equation (4) shows that ##EQU5##
It is readily seen from equation (5) that f.sub.mc is approximately proportional to the square of f.sub.des, and approximately inversely proportional to .DELTA.f. Therefore, in a system which has, for example, an octave frequency range, and in which it is desired that .DELTA.f remain constant, either (1) the high frequency clock must be variable in a precision manner, or (2) additional divider stages and an even higher frequency clock are necessary. In some applications, neither of the above is a desirable method because of cost, parts-count and reliability considerations. Also, as the number of counter stages increases, higher speed counting devices must be used, normally meaning devices which dissipate more power.
Combining Equations (1) and (5) yields: ##EQU6##
It is therefore apparent that the divide ratio, N, is proportional to the desired frequency and inversely proportional to the frequency resolution. If a frequency synthesizer is used, for example, in a conventional 1200 b.p.s. modem, the desired frequencies will be 1200 Hz and 2400 Hz and the desired frequency resolution may be approximately 3.25 Hz. Equation (6) therefore shows that N equals 368.23 if the desired frequency is 1200 Hz, and N equals 737.46 if the desired frequency is 2400 Hz. Rounding N to 368 and 737, respectively, rearranging Equation (1) to solve for f.sub.mc, and inserting the above values of f.sub.des and N, reveals the following results:
TABLE I ______________________________________ Frequency and Divide Ratio Relationships f.sub.des .DELTA.f f.sub.mc N ______________________________________ 1200 3.25 0.4416 MHz 368 2400 3.25 1.7688 MHz 737 ______________________________________
A typical system will use only one master clock frequency and f.sub.mc must be a sufficiently high frequency to obtain the desired frequency resolution at the highest desired frequency. Table I indicates that f.sub.mc equals 1.7688 MHz. Equation (1) therefore requires N to equal 1474 to obtain the lower desired frequency of 1200 Hz. An N of 1474 will require eleven counter stages to divide f.sub.mc down to f.sub.des. At f.sub.mc equals 1.7688 MHz and f.sub.des equals 1200 Hz, changing N by 1 (change in least significant control bit) will, from Equation (4), produce a frequency change of 3.25 Hz. However, at f.sub.des equals 1200 Hz, a change in the least significant bit will now produce a frequency change of 0.81 Hz. To obtain the same desired frequency change at 1200 Hz, N must change not by 1, but by 4 for each step. This requires that the control information be introduced at a higher stage (third least significant bit) to obtain a constant frequency resolution.
Therefore, in the given example, where it is desired to employ a frequency synthesizer with an approximately constant frequency resolution over an octave range of desired frequency while using a single master clock frequency, it will be necessary to use an eleven stage counter and be able to shift the point where the divide control information must be applied from the least significant bit stage to the third least significant bit stage. To be able to shift this point from one stage to another requires either additional logic circuitry or two additional control lines. Additional logic circuitry has the undesirable effects of requiring additional power, generating additional heat, decreasing system reliability, and requiring additional space. Additional control lines have the undesirable effects of requiring more space and requiring a controller to perform additional instructions, thereby decreasing its overall performance and speed.
Furthermore, the output obtained by using a conventional divide-by-N circuit is extremely asymmetrical and is therefore unusable in a phase locked loop. One method that may be used to obtain a symmetrical output is to double the master clock frequency and add an additional divide-by-2 stage at the end of the counter. In this typical example, f.sub.mc would then be 3.5376 MHz and twelve counter stages would be required. It is well known that the power consumed and the heat generated by logic circuitry increases approximately proportionatey to the square of the clock frequency, so doubling the clock frequency has roughly quadrupled the power required and heat generated. Furthermore, the ability to use a lower speed clock allows somewhat slower, low power CMOS devices to be used. Also, slower logic families tend to be less expensive. It is advantageous to keep the clock frequency as low as possible.